SIMULATION METHODOLOGY FOR ANALYZING THE PERFORMANCE OF TFET THROUGH THM-TFET MODEL FILE IN CADENCE

Authors

  • Sri Ch.Pavan Kumar Electronics and Communication Engineering, Kakatiya Institute of Technology and Science Warangal Telangana, India
  • Gorantala Roshini Electronics and Communication Engineering, Kakatiya Institute of Technology and Science Warangal Telangana, India
  • Bolloju Pravalika Electronics and Communication Engineering, Kakatiya Institute of Technology and Science Warangal Telangana, India
  • Khansa Simran Electronics and Communication Engineering, Kakatiya Institute of Technology and Science Warangal Telangana, India
  • Nimmakuri Deepthi Electronics and Communication Engineering, Kakatiya Institute of Technology and Science Warangal Telangana, India

Keywords:

TFET, DG-TFET, THM-TFET

Abstract

MOSFETs are used to create the majority of real-time devices at present due to their fast-switching times. MOSFET subthreshold swing scaling cannot be 60mV/decade lowered. Because of its low subthreshold swing and low leakage current, tunnel FET (TFET) is a viable MOSFET substitute. This paper shows the simulation of the TFET inverter using cadence virtuoso by using the model file called THM-TFET, it is Verilog-A coded and used for the DC and AC simulations of Tunnel FET(TFET).

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Published

2023-12-30

Issue

Vol. 23 (2023): The Journal Punjab Academy of Sciences

Section

Articles

How to Cite

SIMULATION METHODOLOGY FOR ANALYZING THE PERFORMANCE OF TFET THROUGH THM-TFET MODEL FILE IN CADENCE. (2023). JOURNAL PUNJAB ACADEMY OF SCIENCES, 23, 95-100. https://jpas.in/index.php/home/article/view/56

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