Performance Assessment of III-V Heterojunction FinFETs at 14nm Gate Length

Authors

  • Pooja Sharma
  • Navneet Kaur
  • Gurpurneet Kaur

Keywords:

FinFET, heterojunction, Subthreshold swing, fin height, fin width, TCAD.

Abstract

Fin shaped field effect transistors have become prominent candidate in high-performance processors of leading semiconductor industries. It is owing to the fact that thin fin of structure and presence of gates on multiple sides increase electrostatic integrity. Objective of the present work is to design FinFET for gate length of 14nm and analyse performance parameters for different channel materials. Fin width and fin height of device is set as 7nm and 12nm; 25nm and 30nm respectively. Channel of FinFET has been structured with III-V type materials such as AlGaAs, InGaAs and InP. Cogenda Visual TCAD tool has been used for accurate design and extensive simulations of FinFET. Performance has been investigated in terms of on-current (Ion), leakage current (Ioff) and subthreshold swing (SS) for applied drain voltage and gate voltage. These parameters have been extracted from current-voltage characteristics of the device. Ion/Ioff is of the order 107, Ioff is of the order 10-14 and SS is around 80mV/dec for InP material. Based on performance comparison, it is noted that superior performance is achieved in case of InP material as compared to other materials. 

References

Aujla, S.K. 2022. Optimization of Dual-K Gate Dielectric and Dual Gate Heterojunction SOI FinFET at 14nm Gate Length. IETE J Res. 68: 658-666.

Colinge, J.P. 2008. FinFETs and Other Multi-Gate Transistors. Springer.

Das, R. 2016. Tri-gate heterojunction SOI Ge-FinFETs. Superlattices Microstruct.91:51-61.

Dharmarasu, N. 2017. Compound Semiconductors. Reference Module in Materials Science and Materials Engineering. Elsevier.

Faber,H. 2017. Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution.Sci Adv.3:e1602640.

Han, K. 2017. Asymmetric drain extension dual-kk trigate underlap FinFET based on RF/Analog circuit. Micromachines, 8: 330.

Hur,J.H. 2016. III–V compound semiconductors for mass-produced nano-electronics: theoretical studies on mobility degradation by dislocation. Sci Rep, 6.

Im,K. -S. 2023. Impact of Fin Width on Low-Frequency Noise in AlGaN/GaN FinFETs: Evidence for Bulk Conduction. IEEE Access, 11: 10384-10389.

Kaur, G. 2020. Whale optimization algorithm for performance improvement of silicon-on-insulator FinFETs. Int J Artif Intell.18:63-81.

Lee,J. H. 2016. Bulk FinFETs: Design at 14 nm Node and Key Characteristics. In: Kyung, CM. (eds) Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting. KAIST Research Series. Springer, Dordrecht.

Lu,W. 2022. Ultrawide Bandgap Nitride Semiconductor Heterojunction Field Effect Transistors. IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), USA. 99-103.

Reddy, M. N. 2023. Performance Analysis of AlGaN/GaN FINFET for Different Temperatures, Gate Oxide dielectric’s and Work functions. Int. Conf. for Advancement in Technology (ICONAT), Goa, India. 1-6.

Robertson, J. 2004. High dielectric constant oxides. EPJ Appl. Phys.28:265–291.

Yanfu, S. 2016. 3D FinFET simulation with Density Gradient (DG) quantum correction model.

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Published

2024-02-28

How to Cite

Pooja Sharma, Navneet Kaur, & Gurpurneet Kaur. (2024). Performance Assessment of III-V Heterojunction FinFETs at 14nm Gate Length. Journal Punjab Academy of Sciences, 23, 296–301. Retrieved from https://jpas.in/index.php/home/article/view/79